Integrated circuits are typically produced with the aid of lithographic process techniques. For a number of circuit planes to be produced on a substrate, a respective mask is produced and used to project the pattern of the plane into a photosensitive layer (resist) on the substrate. By way of example, a projection apparatus that demagnifies the structure elements of the pattern in a ratio of 4:1 or 5:1 is used.
The exposed structures in the resist are subsequently developed so that afterward, in an etching step, the developed structures can be transferred into an underlying layer in which, by way of example, electronic components such as transistors or diodes, doping regions, capacitors, interconnects, or their mutual insulations, etc., are to be formed on the basis of trenches in the layer.
Miniaturization in semiconductor technology has advanced continuously in the past 20 years. Physical limits are imposed on miniaturization by the limited resolution capability, in particular of the projection apparatuses used, with progress continuously being made.
For the quality, however, not only is the minimum width of structure elements that can be obtained on the substrate crucial, but it is also necessary to take account of the uniformity of elements of approximately identical size that are predefined in the layout after an imaging on the substrate. By virtue of a two-stage process—firstly formation of the structure elements on the mask and subsequently on the substrate (e.g. a semiconductor wafer)—the effects of nonuniformity can be intensified in a disadvantageous manner.
This applies particularly when working with line widths, i.e. widths of the structure elements formed, in the range close to the resolution limit of the projection apparatus for the imaging from the mask onto, e.g., a wafer. In the case of line widths on the mask close to the resolution limit of the optical system, a function which relates the line widths respectively resulting in the course of the imaging on the wafer to the initial line widths on the mask becomes nonlinear. Local fluctuations on the mask can therefore lead to considerable line width variations on the substrate. This is referred to as the so-called Mask Error Enhancement Factor (MEEF).
Conversely, variations of line widths of different structure elements that are already formed unintentionally on the mask from the outset in the range have a particularly considerable effect on distributions of the line widths (LB) that correspondingly result on the substrate. A very high degree of uniformity of the line widths (LB) on the mask made available is therefore required.
Currently available techniques for producing structure patterns on masks are based on electron beam writers. However, the latter no longer suffice for the future requirements made of line width uniformity, in the context of which line widths of 50 nm or less are to be obtained after projection on the substrate (semiconductor wafer).
In a manner similar to that in the course of the described structure transfer from the mask into a resist arranged on the substrate, the pattern on the mask is also produced lithographically. However, the pattern is drawn using a high-resolution beam, for instance an electron beam. Masks with less stringent requirements made of the resolution can also be drawn using the laser beam in the ultraviolet wavelength range (at 248 nm or 365 nm).
The patterns drawn in the resist on the mask are transferred into the underlying absorber layer in etching processes, usually by dry etching. In addition to effects that may be brought about by development processes, in particular etching processes for transferring the resist structure into the absorber on the mask are also considered as the cause of fluctuations of the line width. This holds true particularly at the edges and in the corners of the mask substrate which are subject to systematically deviating conditions in the etching process.
This further holds true for the production of photolithographic masks, but arises in a disadvantageous manner in particular in the production of EUV masks (EUV: extreme ultraviolet wavelength range in the range of from approximately 10 to 15 nm, used in the projection of the pattern onto the wafer). In the production of templates for the nano-imprinted technique, these variations of line width considerably restrict the usability of this technique.
One approach for avoiding these disadvantages involves performing a predistortion of the structure elements that is adapted over the region of the mask. This predistortion would have to be calculated in the layout, i.e. the pattern still present in an electronic format. The pattern would then be drawn on the mask with the predistorted layout. The predistortions compensate for the systematic variations of the line width across the region. However, the currently available solutions in terms of hardware and software technology permit this method only to a very limited extent. It would be necessary at any rate to effect renewed adaptation of the layout data after the production of a first reference mask and hence rewriting at the pattern generator, which would in turn result in increased costs since even the first reference mask would have to meet the stringent specifications.